Are you passionate about applying formal verification techniques to ensure the functional correctness of complex digital ASIC designs? We have an exciting opportunity for a Formal Verification Engineer to join a dynamic team, working remotely with occasional visits to the London office.


We are looking for a Formal Verification Engineer to join a cutting-edge Google HPC program.
You will apply formal verification techniques to ensure the correctness and completeness of chiplet-based designs featuring multi-processors and high-speed I/Os, working closely with RTL and DV teams.
Key Responsibilities*Develop and optimize SystemVerilog Assertions (SVA) and formal properties
*Perform formal verification at block, subsystem, and full-chip levels
*Create abstractions, assumptions, and constraints for proofs
*Identify bugs, dead code, unreachable coverage, and vacuous proofs
*Debug counterexamples and proof failures using JasperGold, VC Formal, and Questa Formal
*Collaborate with RTL and DV teams to achieve verification coverage closure
Required Qualifications*BSc or MSc in EE, CE, CS, Mathematics, or Physics
*Strong knowledge of SystemVerilog/Verilog and digital design
*Minimum 5+ years of relevant experience required
*Hands-on experience with formal verification methodologies
*Proficiency with SVA (PSL a plus)
*Experience with at least one formal tool (JasperGold, VC Formal, or Questa Formal)
*Strong debugging and problem-solving skills
Preferred Experience*Semiconductor HPC or complex SoC designs
*AXI, CPU, DSP, DDR, PCIe, or HBM verification
*Familiarity with UVM and simulation-based flows
*Scripting experience (Python, TCL, Perl)
Soft Skills*Strong analytical mindset and attention to detail
*Clear technical communication skills
*Proactive, collaborative, and self-driven