Role Overview:
We are seeking a Principal or Senior Digital IC Design Engineer to play a key role in the design and verification of advanced digital and mixed-signal optical devices.
You will work closely with product definition and cross-functional teams to shape chip architecture, define detailed specifications, and deliver high-quality RTL designs through to tape-out.
This role suits a high-energy, self-motivated engineer who enjoys ownership across the digital design lifecycle, thrives in collaborative, high-performance environments, and is motivated by solving complex digital IC challenges while influencing next-generation product development.


Key Responsibilities:
*Collaborating with the product definition team to develop high-level requirements for new devices.
*Translating architecture documents and high-level specifications into detailed design specifications.
*Creating RTL designs using Verilog or VHDL, performing block and top-level simulations, and applying timing constraints.
*Developing comprehensive verification plans to fully validate designs through simulation.
*Behavioural modelling of complex analogue functions to support mixed-signal integration.
*Executing synthesis, place and route, DFT insertion, timing closure, and ATPG for SCAN test.
*Working closely with layout engineers to ensure designs meet LVS, DRC, and timing requirements.
*Supporting design verification environment definition, implementation, and debugging.
*Mentoring and guiding junior team members to support technical growth and knowledge sharing.


Minimum Qualifications:
Degree in Electrical/Electronic Engineering or related field (BSc/MSc/BEng/MEng/PhD).
Principal: 10+ years’ experience in digital IC design from specification through to tape-out.
Senior: Minimum of 7+ years of relevant digital IC design experience.


Skills Required:
*Proficiency in Verilog or VHDL for RTL design and verification.
*Experience in low-power, energy-efficient digital logic design.
*Knowledge of scripting languages such as Perl, TCL, or similar.
*Expertise with digital design tools for synthesis, place & route, timing closure, DFT insertion, and ECO from Synopsys or Cadence.
*Experience with CMOS process technologies from 180nm down to 28nm or below.
*Proven track record of delivering multiple designs into mass production.


Desired Qualifications:
Verification experience with SystemVerilog, C, or Vera.
Exposure to mixed-signal verification or FPGA design.